`timescale 1ns/1ps

interface exp_intf(input clk, input rstn);
  logic             code            ;
  logic   [11-1:0]  exp1            ;
  logic   [11-1:0]  exp2            ;
  logic             signal_double   ;
  logic   [12-1:0]  exp_out         ;

  clocking drv_ck @(posedge clk);
    default input #1ns output #1ns;
    input exp_out  ;
    output  code, exp1, exp2, signal_double ;
  endclocking
  clocking mon_ck @(posdege clk);
    default input #1ns output #1ns;
    input exp_out, code, exp1, exp2, signal_double  ;
  endclocking

endinterface

module tb_exp;
  logic clk;
  logic rstn;

  exp_handle dut(
     .code(exp_if.code)
    ,.exp1(exp_if.exp1)
    ,.exp2(exp_if.exp2)
    ,.signal_double(exp_if.signal_double)
    ,.exp_out(exp_if.exp_out)
  );

import exp_handle_pkg::*;

exp_intf exp_if(.*);

initial begin
  run_test("exp_data_consistence_basic_test");
end

endmodule










